1. Field of the Invention
The present invention relates to a semiconductor device including a silicon substrate formed with a field oxide for device isolation, and to a manufacturing method thereof.
2. Description of the Related Art
An LSI is formed by disposing a multiplicity of devices on a silicon substrate, and hence each individual device is electrically separated by a field oxide. The field oxide, which has a thickness on the order of several hundred nm to 1 .mu.m, is obtained by selectively oxidizing silicon in a region between the devices on the silicon substrate.
FIG. 2 is a diagram showing processes of a method of manufacturing a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Referring to FIG. 2, the prior art of the method of manufacturing the semiconductor device will hereinafter be described.
To start with, a silicon oxide layer 32, which is 15-20 nm in thickness, is formed by thermal oxidation on a single crystal silicon substrate 31. A silicon nitride layer 33 is deposited in thickness of 400-600 nm on the silicon oxide layer 32 (FIG. 2(a)). Thereafter, a surface of the silicon substrate 31 under the silicon oxide layer 32 is exposed by selective etching of the silicon oxide layer 32 and the silicon nitride layer 33 by use of a resist mask (FIG. 2(b)). Then, an ion implantation is carried out to prevent a parasitic transistor from being formed, and thereafter the silicon substrate 31 is oxidized in an atmosphere containing water at approximately 1000.degree. C. (FIG. 2(C)). At this time, the silicon nitride layer 33 functions as a mask to protect the silicon substrate from permeations of oxygen and water vapor, and therefore the exposed region of the silicon substrate by the etching can be selectively oxidized. Further, the silicon oxide layer 32 formed on the silicon substrate 31 is provided for relieving a stress produced due to a difference in terms of a thermal expansion coefficient between the selectively oxidized silicon and the silicon nitride layer 33. A process of thus oxidizing the surface of the silicon substrate is known as a LOCOS (Local Oxidation Of Silicon) method. Thereafter, the silicon oxide layer 32 and the silicon nitride layer 33 are removed, thereby completing the device separation (FIG. 2(d)).
The silicon oxide layer (hereinafter termed a field oxide layer) 34 formed by the LOCOS method is approximately 1 .mu.m in thickness, which is approximately twice the thickness of the silicon before oxidation. Accordingly, as shown in FIG. 2(d), a region formed with the field oxide layer 34 is higher by one step than the surface of the silicon substrate 31.
Next, a gate 35 is prepared by forming a gate oxide layer 35a, a polysilicon (polycrystalline silicon) gate 35b for a gate electrode, and a tungsten silicide 35c. Then, the ions are implanted into the silicon substrate 31 to form a source/drain region. Subsequently, an oxide layer 36 of PSG (Phosphorous-Silicate-Glass) is deposited by a CVD (Chemical Vapor Deposition) method in a thickness enough to obtain a sidewall length in order to form sidewalls (FIG. 2(e)). Thereafter, the oxide layer 36 is etched by an anisotropic etching process such as RIE (Reactive Ion Etching), thereby sidewalls 37 are formed (FIG. 2(f)). At this time, there must be non-uniformities in the thickness of the oxide layer 36 deposited by the CVD method as well as in an etching speed of the anisotropic etching process, and hence an overetching process must be executed to completely remove the oxide layer 36 on the gate 35 as well as on the silicon substrate 31.
Then, the ion implantation is again implemented to form the source/drain region, and the MOSFET is completed by forming an insulating layer and a contact hole and providing aluminum wiring in normal processes.
According to the prior art method of manufacturing the semiconductor device, as discussed above, the overetching process is executed when forming the sidewall 37. Therefore, simultaneously when the oxide layer 36 is etched, the field oxide layer 34 is likewise etched and thereby reduced in thickness. Accordingly, a field isolation voltage of the field oxide layer 34 decreases, and an inter-device leakage current is increased.
Such being the case, according to the technique disclosed in Japanese Patent Laid-Open Publication No.4-100243, as shown in FIG. 3, the field oxide 34 is formed on the silicon substrate 31 by use of the LOCOS method, and, after forming a gate oxide layer 40 by thermal oxidization, the surface of the gate oxide layer 40 is further nitrided, whereby a nitride oxide layer 42 is formed on the surface of the gate oxide layer 40. Then, a gate 35 and a side-wall 37 are formed on this nitride oxide layer 42.
Thus, the nitride oxide layer 42 is formed as a protective layer on the field oxide layer 34, thereby making it feasible to prevent the field oxide layer 34 from being over-etched when in the sidewall etching process. As illustrated in FIG. 3, however, if the same prior art technology is employed, the nitrified oxide layer 42 is provided also on the gate oxide layer 40, and therefore the thickness of the gate oxide layer 40 is controlled with difficulty, which might lead to a possibility of making control of a performance of the device difficult.
Under such circumstances, Japanese Patent Laid-Open Publication No.4-100243 also discloses such a technique that a nitride oxide layer 42' is, as shown in FIG. 4, formed only on the field oxide 34 and on a boundary between the field oxide 34 and the gate oxide layer 40. Thus, if the nitrified oxide layer 42 is formed on only a part of the surface of the gate oxide layer 40 as well as on a part of the surface of the field oxide layer 34, the thickness of the gate oxide layer 40 under the gate 35 remains unchanged, and hence the problem given above must be obviated.
In order to form the nitride oxide layer 42' on the partial area of the oxide layer, however, after the nitride oxide layer has been formed over the entire surface of the gate oxide layer 40, the nitride oxide layer under the gate 35 must be removed by use of a photolithography process, which conduces to a problem of increasing the number of working processes.